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E2E1022-27-Y4
Semiconductor MSM80C48/49/50 MSM80C35/39/40
Semiconductor CMOS 8-Bit Microcontroller
This MSM80C35/39/40 MSM80C48/49/50,version: Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The OKI MSM80C48/MSM80C49/MSM80C50 are 8-bit, low-power, high-performance microcontrollers implemented in silicon-gate complementary metal-oxide semiconductor technology. Integrated within these chips are 8K/16K/32K bits of mask program ROM, 512/1024/2048 bits of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program memory and data paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction set, thereby optimizing power down, port data transfer, decrement and port float functions. Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages QFP (GSK).
FEATURES
* Lower power consumption enabled by CMOS silicon gate process * Completely static operation * Improved power-down feature * Instruction cycle : 1.36 ms (11 MHz) VCC=4.5 to 6.0 V (MSM80C48/49) 2.5 ms (6 MHz) VCC=3.5 to 6.0 V (MSM80C50) * 111 instructions * All instructions are usable even during execution of external ROM instructions. * Operation facility Addition, logical operations, and decimal adjust * Program memory (ROM) : 1K words 8 bits (MSM80C48) : 2K words 8 bits (MSM80C49) : 4K words 8 bits (MSM80C50) * Data memory (RAM) : 64 words 8 bits (MSM80C48) : 128 words 8 bits (MSM80C49) : 256 words 8 bits (MSM80C50) * Two sets of working registers * External and timer interrupts * Two test inputs * Built-in 8-bit timer counter * Extendable external memory and I/O ports * I/O port Input-output port : 2 ports 8 bits Data bus input-output port : 1 port 8 bits * Single-step execution function * Wide range of operating voltage, from + 2.5 V to + 6 V of VCC * High noise margin action * Compatible with Intel's 8048, 8049 and 8050 * Package 40-pin plastic DIP (DIP40-P-600-2.54) : (MSM80C48-RS) (MSM80C49-RS) (MSM80C50-RS) (MSM80C35RS) (MSM80C39RS) (MSM80C40RS) 44-pin plastic QFP(QFP44-P-910-0.80-2K) : (MSM80C48-GS-2K) (MSM80C49-GS-2K) (MSM80C50-GS-2K) (MSM80C35GS-2K) (MSM80C39GS-2K) (MSM80C40GS-2K) indicates the code number. 1/20
(PORT 2)
8
PORT2 BUS BUFFER 2 or 3
BLOCK DIAGRAM
PORT2 LATCH (LOW4) AND EXPANDER PORT I/O
PORT2 LATCH (HIGH4)
8
HIGHER PROGRAM COUNTER (4)
4
PROGRAM MEMORY (ROM) 1K8bits MSM80C48RS 2K8bits MSM80C49RS 4K8bits MSM80C50RS
INSTRUCTION REGISTER
PLA
Semiconductor
4
4
OSC FREQ
480
TEST1
TIMER/EVENT COUNTER (8)
LOWER PROGRAM COUNTER (8)
BUS LATCH AND LOW PC TEMP REGISTER
BUS BUFFER
8
(DATA BUS PORT)
(8)
ACCUMULATOR (8)
TEMP REG (8)
FLAGS
MULTIPLEXER
ACCUMULATOR LATCH (8)
ARITHMETIC LOGIC UNIT (8)
CONDITIONAL BRANCH LOGIC
TEST0 RAM ADDRESS TEST1 REGISTER INT FLAG0 FLAG1 TIMER FLAG CARRY ACC
REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7
DECODER
8-LEVEL STACK OPTIONAL SECOND REGISTER BANK DATA STORE
ACC Bit TEST
DECIMAL ADJUST
PORT1 BUS BUFFER AND LATCH
8
(PORT 1)
CONTROL AND TIMING
ALE
READ STROBE WRITE STROBE
INT
RESET PROG
EA
XTAL1 XTAL2
PSEN
SS
RD
WR DATA MEMORY (RAM) 648 bits MSM80C48RS 1288 bits MSM80C49RS 2568 bits MSM80C50RS
MSM80C48/49/50, MSM80C35/39/40
INTERRUPT
OSCILLATOR PROM/ PROGRAM XTAL EXPANDER MEMORY STROBE ENABLE ADDRESS LATCH, SINGLE INITIALIZE CPU MEMORY DATA LATCH STEP SEPARATE STROBE CYCLE CLOCK
2/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN CONFIGURATION (TOP VIEW)
37 DB7
36 DB6
35 DB5
XTAL1 XTAL2 RESET SS INT EA RD PSEN WR ALE
2 3 4 5 6 7 8 9 10 11
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
T1 P27 P26 P25 P24 P17 P16 P15 P14 P13 P12 P11 P10 VDD PROG P23 P22 P21 P20 VDD P10 P11 P12 P13 P14 P15 NC P16 1 2 3 4 5 6 7 8 9
34 DB4
33 DB3 32 DB2 31 DB1 30 DB0 29 ALE 28 WR 27 PSEN 26 RD 25 EA 24 INT 23 SS
42 P23
41 P22
40 P21 T1 16
39 P20 VCC 17
DB0 12 DB1 13 DB2 14 DB3 15 DB4 16 DB5 17 DB6 18 DB7 19 VSS 20
P17 10 P24 11
NC 12
P25 13
P26 14
P27 15
T0 18
38 VSS
44 NC
T0
1
40
VCC

43 PROG XTAL1 19
XTAL2 20
NC 21
NC: No-connection pin 40-Pin Plastic DIP 44-Pin Plastic QFP
RESET 22
3/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN DESCRIPTIONS
Symbol P10-P17 (PORT 1) P20-P27 (PORT 2) Type I/O I/O Description 8-bit quasi-bidirectional port 8-bit quasi-bidirectional port The high-order four bits of external program memory addresses can be output from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected. Bidirectional port The low-order eight bits of external program memory address can be output from this port, and the addressed instruction is fetched under the control of PSEN signal. Also, the external data memory address is output, and data is read and written synchronously using RD and WR signals. The port can also serve as either a statically latched output port or a non-latching input port. The input can be tested with the conditional jump instructions JT0 and JNT0. The execution of the ENT0 CLK instruction causes a clock output.
DB0-DB7 (BUS)
I/O
T0 (Test 0)
I/O
T1 (Test 1) INT (Interrupt)
I
The input can be tested with the conditional jump instructions JT1 and JNT1. The execution of a STRT CNT instruction causes an internal counter input. Interrupt input. If interrupt is enabled, INT input initiates an interrupt. Interrupt is disabled after a reset. Also testable with a JNI instruction. Can be used to terminate the power-down mode. (Active "0" level) A signal to read data from external data memory. (Active "0" level) A signal to write data to external data memory. (Active "0" level) This signal is generated in each cycle. It may be used as a clock output. External data memory or external program memory is addressed upon the falling edge. For the external ROM, this signal is used to latch the bus port data upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction. A signal to fetch an instruction from external program memory (Active "0" level) RESET input initialize the processor. (Active "0" level) Used to terminate the power-down mode. A program is executed step by step. This pin can also be used to control internal oscillation when the power-down mode is reset. (Active "0" level) When held at high level, all instructions are fetched from external memory. (Active "1" level) This output strobes the MSM82C43RS I/O expander.
I
RD (Read) WR (Write) ALE Address & Data Latch Clock PSEN Program Store Enable RESET SS (Single Step)
O O O
O I I
EA (External Access) PROG (Expander Strobe)
I O
4/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN DESCRIPTIONS (Continued)
Symbol XTAL1 (Crystal 1) XTAL2 (Crystal 2) VCC VDD VSS Type I O -- -- -- Description One side of the internal crystal oscillator. An external clock can also be input. Other side of the internal crystal oscillator. Power supply pin Standby control input. Normally, "1" level. When set to "0" level, oscillation is stopped and prosessor goes into standby mode. GND
Note: A minimum of two machine cycles are required in RESET pulse duration under the specified power supply and stable oscillator frequency.
5/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Storage Temperature Symbol VCC VI TSTG Condition Ta=25C Ta=25C -- Rating -0.5 to 7 -0.3 to VCC +0.5 -65 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Ambient Temperature Fan Out Symbol VCC Ta N Condition fOSC=DC to 11MHz* -- MOS load TTL load Range +2.5 to +6 -40 to +85 10 1 Unit V C -- --
*
Minimum operating voltage is dependent on frequency.
6/20
Semiconductor MSM80C48/49/50 guaranteed operating range
MSM80C48/49/50, MSM80C35/39/40
Ta=-40 to +85C
(msec) 100
Guaranteed Operating Range
Cycle Time (tCY)
10
1.5MHz
MSM80C40/80C50
6MHz
11MHz MSM80C35/80C48/80C39/80C49 1
2
3
4 Supply Voltage (VCC)
5
6
(V)
7/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "L" Input Voltage "H" Input Voltage *1 "H" Input Voltage *2 "L" Output Voltage *3 "L" Output Voltage *4 "H" Output Voltage *3 "H" Output Voltage *4 "H" Output Voltage *3 "H" Output Voltage *4 Input Leakage Curent Output Leakage Current *5 RESET Input current SS Input current *6 P1, P2 input current Power Down Mode Standby Current Symbol VIL VIH VIH VOL VOL VOH VOH VOH VOH IIL IOL IR ISS IP1, IP2 Condition -- -- -- IOL=2 mA IOL=1.6 mA IOH=-400 mA IOH=-50 mA IOH=-20 mA IOH=-10 mA VSS VIN VCC VSS VO VCC VIN=0.7 VCC VIN=0.13 VCC Pull-up (VIN=VIL) Pull-down (VIN=VIH) VIN=VIH VIN=VIL At hardware power down *7 Ta=25C, VCC=2.0 V At HLTS execution *7 Ta=25C, VCC=2.0 V VCC=4 V, f=1 MHz VCC=4 V, f=6 MHz VCC=4 V, f=11 MHz Power Supply Current (Halt Mode) VCC=5 V, f=1 MHz ICC VCC=5 V, f=6 MHz VCC=5 V, f=11 MHz VCC=6 V, f=1 MHz VCC=6 V, f=6 MHz VCC=6 V, f=11 MHz VCC=4 V, f=1 MHz VCC=4 V, f=6 MHz VCC=4 V, f=11 MHz VCC=5 V, f=1 MHz Power Supply Current ICC VCC=5 V, f=6 MHz VCC=5 V, f=11 MHz VCC=6 V, f=1 MHz VCC=6 V, f=6 MHz VCC=6 V, f=11 MHz (VCC=5 V10%, Ta=-40 to +85C) Min. -0.5
0.4 VCC 0.7 VCC
Typ. -- -- -- -- -- -- -- -- -- -- -- -50 -8 50 -15 -600 -40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. Unit suring
0.13 VCC
Mea-
Circuit
V V V V V V V V V mA mA mA mA mA mA mA mA mA 2 2 2 3 1
VCC VCC 0.45 0.45 -- -- -- -- 5 5 -80 -15 80 -25 -900 -80 10 10 0.5 1.0 2.0 1.0 2.0 3.0 1.5 3.0 5.0 1.5 5.0 10 2.5 7.5 15 5.0 10 20
-- --
0.75 VCC 0.75 VCC 0.93 VCC 0.93 VCC
-- -- -20 -3 20 -6 -300 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ICCS
mA
4
mA
8/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
*1 *2 *3 *4 *5 *6 *7
This does not apply to RESET, XTAL1, XTAL2, VDD, and EA. RESET, XTAL1, XTAL2, VDD, and EA. BUS, RD, WR, PSEN, ALE, PROG Other outputs High-impedance state This operates as a pull-down resistor when the oscillation is stopped in the HLTS or VDD power-down mode and as a pull-up resistor in other states. This does not contain flow out current from I/O ports and signal pins.
9/20
Semiconductor AC Characteristics
MSM80C48/49/50, MSM80C35/39/40
(VCC=2.5V to 6V (*1), Ta=-40 to +85C) VCC=5 V10% Parameter ALE Pulse Width Address Setup Time (up to ALE) Address Hold Time (from ALE) Bus Port Latch Data Setup Time (up to ALE Rising Edge) Bus Port Latch Data Hold Time (from ALE Rising Edge) Control Pulse Width (RD, WR) Control Pulse Width (PSEN) Data Setup Time (before WR) Data Hold after Time (after WR) Data Hold Time (after RD, PSEN) RD to Data-in PSEN to Data-in Address Setup to WR Address Setup to Data-in Address Setup to Instruction Address Float to RD, WR Address Float to PSEN Control Pulse Setup Time from ALE (PSEN) Control Pulse Setup Time from ALE (RD, WR) Control Pulse up to ALE (RD, WR, PROG) Control Pulse up to ALE (PSEN) Port Control Setup Time (up to PROG Falling Edge) Port Control Hold Time (from PROG Falling Edge) PROG to Input Data Valid Input Data Hold Time Output Data Setup Time Output Data Hold Time PROG Pulse Width Port 2 I/O Setup Time Port 2 I/O Hold Time Port Output Data (from ALE) T0 Cycle Instruction Execution Time Symbol 11 MHz Clock Min. Max. tLL tAL tLA tBL tLB tCC1 tCC2 tDW tWD tDR tRD1 tRD2 tAW tAD1 tAD2 tAFC1 tAFC2 tLAFC2 tLAFC1 tCA1 tCA2 tCP tPC tPR tPF tDP tPD tPP tPL tLP tPV tOPRR tCY 150 70 50 110 90 480 350 390 40 0 -- -- 300 -- -- 140 10 60 200 50 320 50 100 -- 0 250 40 700 160 15 -- 270 1.36 -- -- -- -- -- -- -- -- -- 110 350 190 -- 730 460 -- -- -- -- -- -- -- -- 650 140 -- -- -- -- -- 510 -- -- Variable clock 0 to 11 MHz Min. Max. 3.5t-170 2t-110 t-40 2.5t -115 1.5 t-45 7t-155 6t-200 6t-155 2t-140 0 -- -- 6t-245 -- -- 2t-40 10 t-30 3t-75 1.5t-85 4.5t-90 2t-130 4t-260 -- 0 6t-290 3t-230 10t-210 4.5-250 1.5t-120 -- 3t 15t -- -- -- -- -- -- -- -- -- 1.5t-30 5t-265 5t-265 -- 12t-360 8t-265 -- -- -- -- -- -- -- -- 9t-170 1.5t -- -- -- -- -- 4t+145 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note : Control output : CL=80pF Bus output : CL=150pF [for 20 pF (tAL, tAFC1, tAFC2)] *1 Minimum operating voltage is dependent on frequency.
10/20
Semiconductor Measuring circuits
1
MSM80C48/49/50, MSM80C35/39/40
2
VCC OUTPUT INPUTS VIH VIL (*3)
(*2)
(*1) INPUTS
VCC OUTPUT
V
A IO
A
GND
GND
3
4
A
VCC OUTPUT INPUTS VIH VIL (*3) VIH A VIL (*3) INPUTS
VCC OUTPUT
GND
GND
5
VCC VIH VIL OUTPUT INPUTS (*3)
(*2) CL
VIH I VOH O O VOL tXXX tXXX VOL VOH VIL
GND
*1 This is repeated for each specified input pin. *2 This is repeated for each specified output pin. *3 Input logic for setting the specified state
11/20
Semiconductor Timing Diagram
MSM80C48/49/50, MSM80C35/39/40
Instruction fetch (from external program memory)
tCY tLL
ALE
tAFC tCC
PSEN
tAL tLA tRD
FLOATING
tDR
INSTRUCTION
tBL
tLB
ADDRESS
BUS
LATCH DATA
ADDRESS
LATCH DATA
tAD
Read (from external data memory)
ALE
tCC
RD
tAFC tRD tDR
DATA
FLOAT- ADDRESS ING
BUS
ADDRESS
FLOATING
tAD
12/20
Semiconductor Write (to external memory)
MSM80C48/49/50, MSM80C35/39/40
ALE
tCC
WR
tAW tDW
FLOATING DATA
tWD
ADDRESS
BUS
ADDRESS
Low-order 4 bits input/output of port 2 when expanded I/O port is used (in external program memory access mode)
ALE
tPL tLP PORT CONTROL tPR tDP OUTPUT DATA tPF INPUT DATA tPP tPD
P20-3 (Output mode)
PCH
PORT DATA
P20-3 (Input mode)
PCH
PORT DATA
PORT CONTROL tCP tPC
PROG
13/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
FUNCTIONAL DESCRIPTION
Added Functions of MSM80C48, MSM80C49 and MSM80C50 The MSM80C48, MSM80C49 and MSM80C50 are basically incorporated with the capabilities of Intel's 8048, 8049, and 8050 plus the following new functions: 1. Power-Down Mode Enhancements
1.1 Power-down by software (1) Clock (See item 4, "Power-down mode", for details.) a. Crystal oscillator halt (HLTS instruction) Power requirements can be minimized. b. Clock supply halt (HALT instruction) Restart is accomplished without oscillator wait. (2) I/O ports I/O port floating instructions Power consumption resulting from inputs/outputs can be minimized with FLT and FLTT instructions. Port floating is cancelled by executing FRES instruction, "0" level at INT pin or "0" level at RESET pin. (3) Six types of power-down can be done by a combination of HLTS/HALT and FLT/FLTT instructions. 1.2 Power-down by hardware (See 4.3, Power-down mode by VDD pin utilization for details.) Crystal oscillators can be halted by controlling the VDD pin, thereby floating all I/O ports for minimum power consumption. 2. Additional Instructions (11) HLTS MOV A, P2 HALT MOVP1, @ R3 FLT MOVP1 P, @R3 FLTT DEC @Rr FRES DJNZ @ Rr, addr MOV A, P1 Improved Uses of BUS P0-7, P10-7, P20-7, and SS pins
3.
3.1 BUS P0-7 The MSM80C48, MSM80C49, and MSM80C50 remove the limitation on the use of OUTL BUS, A instructions during the external ROM access mode by having an independent data latch and external ROM mode address latch in BUS P0-7. Consequently, there is no need to relocate bus port instructions when in the external ROM access mode. 3.2 P10-7 and P20-7 The MSM80C48, MSM80C49 and MSM 80C50 are designed to minimize power consumption when P10-7 and P20-7 are used as input/output ports, to maximize the performance of CMOS. When these ports are used as output ports, the acceleration circuit is actuated only when 14/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
output data changes from "0" to "1", thus speeding up the rise time of the output signals. When these ports are used as input ports, the internal pull-up resistor becomes approximately 9 kW when input data is "1". The internal pull-up resistor rises to approximately 100 kW when input data is "0". Thus, a high noise margin can be obtained by selecting the impedance and thus the outflow of current is minimized whenever these ports are used as output or input ports. 3.3 Clock generation control via the SS pin When the crystal oscillator is halted in the HLTS or hardware power-down mode, the SS pin is pulled down by a resistor of 20 to 50 kW, while its internal pull-up resistor of 200 to 500kW is isolated from VCC. When the power-down mode is cancelled, the internal resistor of the SS pin is changed from pull-down to pull-up. Consequently, the CPU can be halted for any period of time until the crystal oscillator resumes normal oscillation when a capacitor is connected to the SS pin. 4. Power-Down Mode The MSM80C48, MSM80C49, and MSM80C50 power-down mode can be enabled in two different ways through software by a combination of clock control and port floating instructions, and through hardware by control of the VDD pin.
4.1 Software power-down mode Power-down mode can be done by a combination of the following instructions. (1) HALT (clock supply halt to control circuit) Instruction code : 0 0 0 0 0 0 0 1 Although crystal oscillator operation is continued, the clock supply to the CPU control circuit is halted and CPU operations are suspended. When cancelling this software mode, restart is accomplished without oscillator wait. (2) HLTS (oscillation stop) Instruction code : 1 0 0 0 0 0 1 0 The oscillator operation is halted and CPU operations are suspended. In cancelling this power down mode, connecting a capacitor to the SS pin enables a reasonable wait period to be accomplished before normal operation is resumed. [Except in the case of using the RESET pin] (3) FLT (floating P10-7, P20-7, and BP0-7) Instruction code : 1 0 1 0 0 0 1 0 Description :
P1 P2 BP
Description :
Description :
Internal ROM mode Floating Floating Floating
External ROM mode Floating P20-3 operation Operation
15/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
Details of IC pin status as a result of executing the FLT instruction are shown in the above table. (4) FLTT (floating of all output pins) Instruction code : 1 1 0 0 0 0 1 0
Internal ROM mode External ROM mode Operation Operation Floating Floating Floating Floating Floating P20-3 operation Operation Operation
Description :
ALE PSEN PROG WR PD T0 OUT P1 P2 BP XTAL
Floating Floating Floating Floating Floating Floating Floating Floating Floating Operation
Details of IC pin status as a result of executing the FLTT instruction are shown in above Table. Example 1 : Power-down mode accomplished by stopping oscillation. m Can be set by execution of HLTS [82H] instruction. Example 2 : Power-down mode accomplished by stopping the clock supply to the CPU control circuit. m Can be set by execution of HALT [01H] instruction. Example 3 : Power-down mode by floating of P10-7, P20-7 and BP0-7, and subsequent stopping of CPU oscillation. m Can be set by first executing the FLT [A2H] instruction, followed by the HLTS [82H] instruction. Example 4 : Power-down mode by floating P10-7, P20-7 and BP0-7, and then stopping the clock supply to the CPU control circuit. m Can be set by first executing the FLT [A2H] instruction, and then the HALT [01H] instruction. Example 5 : Power-down mode by floating all output pins, followed by stopping oscillation. m Can be set by first executing the FLTT [C2H] instruction followed by execution of the HLTS [82H] instruction. Example 6 : Power-down mode by floating all output pins, followed by stopping of the clock supply to the CPU control circuit. m Can be set by first executing the FLTT [C2H] instruction, followed by execution of the HALT [01H] instruction. Connect the pull-up resistor or pull-down resistor to port pin and fix the output port pin level to either 1or 0 when output port is set to floating.
16/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
4.2 Cancellation of software power-down mode The power-down mode status outlined above in examples 1 to 6 can be cancelled by using either the interrupt pin or the RESET pin. (1) Use of the INT pin during external interrupt enable mode (i.e. following execution of EN I instruction). m The clock generator is activated and the CPU is started up when a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, an external interrupt is generated, and execution proceeds from address 3. If, however, the power-down is entered during the interrupt processing routine, execution resumes just after the power-down instruction. (2) Use of the INT pin during external interrupt disable mode (i.e. following execution of DIS I instruction or hardware reset) m The clock generator is activated and the CPU is started up when a "0" level is applied to the INT pin. When "0" level is maintained until the occurrence of at least 2 ALE output signals, execution is resumed just after the power-down instruction. (3) Use of the RESET pin m The clock generator is activated and the CPU started up when a "0" level is applied to the RESET pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, the CPU is reset and execution proceeds from address 0. In case cancellation is done in oscillation stop mode, the "0" level must be input to the RESET pin until oscillation is stabilized.
17/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
4.3 Hardware power-down mode In the MSM80C48, MSM80C49 and MSM80C50, forcing the level at the VDD pin to a "0" during either external ROM or internal ROM mode results in suspension of the oscillator function and subsequent floating (high impedance) of all the I/O pins except the RESET, SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status. 4.4 Cancellation of hardware power-down mode (1) Use of RESET pin m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is input to the RESET pin. If this "0" level is kept applied to the RESET pin until oscillation become stable, the CPU will be reset and will start executing from address 0. (2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN I instruction) m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, an external interrupt is generated, and execution starts from address 3. However, if the power-down mode is started during an interrupt processing routine, execution will be continued on the next instruction after the present instruction. (3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS I instruction or hardware reset) m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "0" level is applied to the INT pin. If this "0" level is maintained until the occurrence of at least 2 ALE output signals, execution is continued on the next instruction after the present instruction. (4) Use of VDD pin only m The clock generator is activated and the CPU started up when a "1" level is applied to the VDD pin while a "1" level is also applied to both the RESET and INT pins. In this case, execution is resumed from the stopped position.
18/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
19/20
Semiconductor
MSM80C48/49/50, MSM80C35/39/40
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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